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TitlePhase-Locking in High-Performance Systems: From Devices to Architectures
ISBN 139780471447276
File Size41.1 MB
Total Pages512
Table of Contents
                            Table of Contents
Original Contributions
PLLs in High Performance Systems_Papers.pdf
	Phase noise and Jitter.pdf
		A study of phase noise in CMOS oscillators
		Corrections to-A General Theory of Phase Noise in Electrical Oscillators
		Jitter and phase noise in ring oscillators
		On-Chip Measurement of the Jitter Transfer Function of Charge-Pump Phase-Locked Loops
		Physical processes of phase noise in differential LC oscillators
		A general theory of phase noise in electrical oscillators
		A study of oscillator jitter due to supply and substrate noise
	RF Synthesis.pdf
		RF Synthesis.pdf
			A 2-V 900-MHz Monolithic CMOS Dual-Loop Frequency Synthesizer for GSM Receivers.pdf
			A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mbps GFSK modulation.pdf
			A CMOS Frequency Synthesizer with an Injection-Locked Frequency Divider for a 5-GHz Wireless LAN Receiver.pdf
			A Fully Integrated CMOS Frequency Synthesizer with Charge-Averaging Charge Pump and Dual-Path Loop Filter for PCS.pdf
			A modeling approach for spl Sigma-spl Delta fractional-N frequency synthesizers allowing straightforward noise analysis.pdf
			A Stabilization Technique for Phase-Locked Frequency Synthesizers.pdf
			An Adaptive PLL Tuning System Architecture Combining High Spectral Purity and Fast Settling Time.pdf
			Fast Switching Frequency Synthesizer with a Discriminator-Aided Phase Detector.pdf
			Low-Power Dividerless Frequency Synthesis Using Aperture Phase Detection.pdf
			A 1.8-GHz Self-Calibrated Phase-Locked Loop with Precise I Q Matching.pdf
			A 2.6-GHz OR 5.2-GHz Frequency Synthesizer in 0.4 um CMOS Technology.pdf
			A CMOS monolithic sigmadelta-controlled fractional-N frequency synthesizer for DCS-1800.pdf
	Clock Generation by PLLs and DLLs.pdf
		A 960-Mbps per pin interface for skew-tolerant bus using low jitter PLL.pdf
		A dual-loop delay-locked loop using multiple voltage-controlled delay lines.pdf
		A low jitter 0.3-165 MHz CMOS PLL frequency synthesizer for 3 V or 5 V operation.pdf
		A Low-Jitter PLL Clock Generator for Microprocessors with Lock Range of 340-612 MHz.pdf
		A Low-Jitter Wide-Range Skew-Calibrated Dual-Loop DLL Using Antifuse Circuitry for High-Speed DRAM.pdf
		A low-noise fast-lock phase-locked loop with adaptive bandwidth control.pdf
		A Portable Digital DLL for High-Speed CMOS Interface Circuits.pdf
		A Register-Controlled Symmetrical DLL for Double-Data-Rate DRAM.pdf
		A Semidigital Dual Delay-Locked Loop.pdf
		A Wide-Range Delay-Locked Loop with a Fixed Latency of One Clock Cycle.pdf
		Active GHz clock network using distributed PLLs.pdf
		Active GHz clock network using distributed PLLs-conf.pdf
		An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance.pdf
		CMOS DLL-Base 2-V 3.2-ps Jitter 1-GHz Clock Synthesizer and Temperature-Compensated Tunable Oscillator.pdf
		Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques.pdf
		A 1.5V 86 mW per ch 8-Channel 622-3125-Mbps per ch CMOS SerDes Macrocell with Selectable Mux or Demux Ratio.pdf
		A 320 MHz, 1.5 mW @ 1.35 V CMOS PLL for Microprocessor Clock Generation.pdf
	Building Blocks.pdf
		A Fully Integrated VCO at 2 GHz
		A Simple Precharged CMOS Phase Frequency Detector
		A 10-Gb/s CMOS Clock and Data Recovery Circuitwith a Half-Rate Linear Phase Detector
		A 40-Gb/s Integrated Clock and Data RecoveryCircuit in a 50-GHz Silicon Bipolar Technology
		A Fully Integrated VCO at 2 GHz
		A Simple Precharged CMOS Phase Frequency Detector
		Rotary Traveling-Wave Oscillator Arrays:A New Clock Technology
		A 1.6-GHz Dual Modulus Prescaler Using the ExtendedTrue-Single-Phase-Clock CMOS Circuit Technique (E-TSPC)
		A CMOS Monolithic -Controlled Fractional-NFrequency Synthesizer for DCS-1800
		A Family of Low-Power Truly Modular Programmable Dividersin Standard 0.35-m CMOS Technology
		A 10-Gb/s CMOS Clock and Data Recovery Circuitwith a Half-Rate Linear Phase Detector
		A 10Gb/s CMOS Clock and Data Recovery Circuitwith Frequency Detection
		A 40-Gb/s Integrated Clock and Data RecoveryCircuit in a 50-GHz Silicon Bipolar Technology
		A Fully Integrated 40-Gb/s Clock and Data RecoveryIC With 1:4 DEMUX in SiGe Technology
	Clock and Data Recovery.pdf
		Clock and Data Recovery.pdf
			A 10-Gbps CMOS clock and data recovery circuit with a half-rate linear phase detector.pdf
			A 10-Gbps CMOS Clock and Data Recovery Circuit with Frequency Detection.pdf
			A 40-Gbps integrated clock and data recovery circuit in a 50-GHz f t silicon bipolar technology.pdf
			A Fully Integrated 40-Gbps Clock and Data Recovery IC With 1 4 DEMUX in SiGe Technology.pdf
			A fully integrated SiGe receiver IC for 10-Gbps data rate.pdf
			Clock and Data Recovery IC for 40-Gbps Fiber-Optic Receiver.pdf
			Clock Data Recovery PLL Using Half-Frequency Clock.pdf
			SiGe clock and data recovery IC with linear-type PLL for 10-Gbps SONET application.pdf
			A 2-1600-MHz CMOS clock recovery PLL with low-Vdd capability.pdf
			A 2.5-Gbps clock and data recovery IC with tunable jitter characteristics for use in LANs and WANs.pdf
			A 10-Gbps CDR or DEMUX with LC delay line VCO in 0.18-spl mu per m CMOS.pdf
			A 0.5-µm CMOS 4.0-Gbps serial link transceiver with data recovery using oversampling.pdf
Document Text Contents
Page 1


Preface xi

About the Author xiii

Part I Original Contributions

Devices and Circuits for Phase-Locked Systems 3
B. Razavi

Delay-Locked Loops—An Overview 13
C-K. Ken Yang

Delta-Sigma Fractional-TV Phase-Locked Loops 23
/. Galton

Designing Bang-Bang PLLs for Clock and Data Recovery in Serial Data Transmission Systems 34
R. C. Walker

Predicting the Phase Noise and Jitter of PLL-Based Frequency Synthesizers 46

K. S. Kundert

Part II Devices

Physics-Based Closed-Form Inductance Expression for Compact Modeling of Integrated Spiral Inductors 73
S. Jenei, B. K. J C. Nauwelaers, and S. Decoutere {IEEE Journal ofSolid-State Circuits, January 2002)
The Modeling, Characterization, and Design of Monolithic Inductors for Silicon RF IC's 77
J R. Long and M. A. Copeland {IEEE Journal of Solid-State Circuits, March 1997)

Analysis, Design, and Optimization of Spiral Inductors and Transformers for Si RF IC's 89
A. M. Niknejad, and R. G. Meyer {IEEE Journal of Solid-State Circuits, October 1998)

Stacked Inductors and Transformers in CMOS Technology 101
A. Zolfaghari, A. Chan, and B. Razavi {IEEE Journal of Solid-State Circuits, April, 2001)

Estimation Methods for Quality Factors of Inductors Fabricated in Silicon Integrated Circuit
Process Technologies 110
K. O {IEEE Journal of Solid-State Circuits, August 1998)

A Q-Factor Enhancement Technique for MMIC Inductors 114
M. Danesh, J. R. Long, R. A. Hadaway, and D. L. Harame {Dig. IEEE Radio Frequency Integrated Circuits
Symposium, April 1998)

On-Chip Spiral Inductors with Patterned Ground Shields for Si-Based RF IC's 118
C. Patrick Yue and S. S. Wong {IEEE Journal of Solid-State Circuits, May 1998)

Page 2

The Effects of a Ground Shield on the Characteristics and Performance of Spiral Inductors 127
S.-M. Yim, T. Chen, and K. O {IEEE Journal of Solid-State Circuits, February 2002)

Temperature Dependence of Q and Inductance in Spiral Inductors Fabricated in
a Silicon-Germanium/BiCMOS Technology 135
R. Groves, D. L. Harame, and D. Jadus (IEEE Journal of Solid-State Circuits, September 1997)

Substrate Noise Coupling Through Planar Spiral Inductor 140
A. L Pun, T. Yeung, J Lau, E J R. Clement, and D. K. Su (IEEE Journal of Solid-State Circuits, June 1998)

Design of High-g Varactors for Low-Power Wireless Applications Using a Standard CMOS Process 148
A.-S. Porret, T. Melly, C C Enz, and E. A. Vittoz. (IEEE Journal of Solid-State Circuits, March 2000)

On the Use of MOS Varactors in RF VCO's 157

P. Andreani and S. Mattisson (IEEE Journal of Solid-State Circuits, June 2000)

Part III Phase Noise and Jitter

Low-Noise Voltage-Controlled Oscillators Using Enhanced LC-Tanks 165
J. Craninckx and M. Steyaert (IEEE Transactions on Circuits and Systems-II, December 1995)
A Study of Phase Noise in CMOS Oscillators 176
B. Razavi (IEEE Journal of Solid-State Circuits, March 1996)

A General Theory of Phase Noise in Electrical Oscillators 189
A. Hajimiri, andT.H Lee (IEEE Journal of Solid-State Circuits, February 1998)

Physical Processes of Phase Noise in Differential LC Oscillators 205
J. J. Rael, and A. A. Abidi (IEEE Custom Integrated Circuits Conference, May 2000)

Phase Noise in LC Oscillators 209
K. A. Kouznetsov and R. G. Meyer (IEEE Journal of Solid-State Circuits, August 2000)

The Effect of Varactor Nonlinearity on the Phase Noise of Completely Integrated VCOs 214
JWM. Rogers, J A. Macedo, and C Plett (IEEE Journal of Solid-State Circuits, September 2000)

Jitter in Ring Oscillators 221
JA. McNeill (IEEE Journal of Solid-State Circuits, June 1997)

Jitter and Phase Noise in Ring Oscillators 231
A. Hajimiri, S. Limotyrakis, andT. H Lee (IEEE Journal of Solid-State Circuits, June 1999)

A Study of Oscillator Jitter Due to Supply and Substrate Noise 246
E Herzel, and B. Razavi (IEEE Transactions on Circuits and Systems-II, January 1999)

Measurements and Analysis of PLL Jitter Caused by Digital Switching Noise 253
P. Larsson (IEEE Journal of Solid-State Circuits, July 2001)

On-Chip Measurement of the Jitter Transfer Function of Charge-Pump Phase-Locked Loops 260

B. R. Veillette, and G. W.Roberts (IEEE Journal ofSolid-State Circuits, March 1998)

Part IV Building Blocks

A Low-Noise, Low-Power VCO with Automatic Amplitude Control for Wireless Applications 271
M.A. Margarit, J. L. Tham, R. G Meyer, and M. J. Been (IEEE Journal of Solid-State Circuits, June 1999)
A Fully Integrated VCO at 2 GHz 282
M. Zannoth, B. Kolb, J. Fenk, and R. Weigel (IEEE Journal of Solid-State Circuits, December 1998)


Page 256


Fig. 13. Phase and byte sync block diagram.

Fig. 14. Sampler circuit diagram.

step change at the supply, the level settles to


with a time constant of


At the instant of supply step change, the voltage difference
between and remains the same due to the capacitor
at the generator. If - is �xed, the delay cells run
a little bit faster due to the supply voltage increase instead
of keeping exact constant delay. Since - remains the
same temporarily, the delay cells run a little bit faster due

to the increased supply voltage for a short period of time.
And the voltage swing at the VCO increases with a time
constant determined by and OPAMP bandwidth
and approaches to


which result in the increase of one stage delay. This gives
an averaging effect on the VCO delay after the supply step
change, making the delay change minimized with supply step
change. If we select and values for a minimum
average delay change, the effect of supply step change can be
nulli�ed. The values we chose for this particular process are

k k and pF.

Page 257


PLL circuits can be sensitive to noise pickup from the
supplies and substrate. So the PLL circuit has a dedicated
power and ground pads. Bypass capacitors are included in the
layout to stabilize VDD and GND of PLL. Guard rings are
used to isolate PLL and other digital parts. The placement of
multiphase clocks were carefully chosen to remove possible
coupling between clocks.

B. Phase and Byte Sync

Phase and byte sync block at Fig. 1 is shown in Fig 13.
It consists of 3-to-1 mux array, metastability resolver, start
bit �nder, phase memory, word memory, shifter, and D-

ops (DFF's). This circuit �nds the start bit and decimates
the oversampled 12 b and aligns the byte boundary. The
oversampled 12 b are sent from the sampler to the metastability
resolver. Since the oversampled 12 b are not sampled at
the center of the eye, there is a possibility that some of
the bits are still at the metastable state. The metastability
is practically removed by one more stage of synchronizers
in the metastability resolver. The start bit �nder receives
information from the metastability resolver and selects one
of the three phases as a correct phase and also extracts byte
align information. The phase and byte align information are
stored at the phase and word memory. The 3-to-1 mux array
decimates 12 b into 4 b. The shifter at the �nal stage aligns
the byte boundary according to the value of the word memory.

C. Oversampler

The oversampler used in the data receiver is shown in
Fig. 14. Each oversampler is a cascaded sense ampli�er and
uses four clocks for correct, timely sampling. It is very
important to reduce the probability of metastability by careful
design and layout. The same size is used for both PMOS and
NMOS in the core synchronizing ampli�er to maximize the
loop bandwidth.


Two prototype chips, master and slave, have been fabricated
in a 0.6- m double-metal CMOS process. Fig. 15 shows the
microphotograph of the fabricated master chip. This chips
occupies 4100 m 4300 m including pad area. The master
chip incorporates a common skew-insensitive I/O macro block,
a bus protocol handler, and a self-test circuit for chip and
system diagnostics. The common skew-insensitive I/O macro
block includes a charge-pump PLL for multiphase generation,
oversamplers, I/O buffers, parallel-to-serial converters, and a
bias generator for internal use. The core area for the skew-
insensitive I/O macro block is 3600m 700 m for 4-pin
interface. The microphotograph of the fabricated slave chip
is shown in Fig 16. It has the same die size as the master
chip. Many blocks are shared with the master chip. The skew-
insensitive I/O macro block and the charge pump PLL are the
same as those of the master's. The slave chip includes a small
internal fast SRAM to verify correct read/write operations.

The measured charge pump PLL jitter histogram of the
master and the slave chips is shown in Fig. 17. Since the two
chips use the same PLL, it showed similar jitter performance.

Fig. 15. Microphotograph of master chip.

Fig. 16. Microphotograph of slave chip.

The rms jitter is 15.7 ps when the tested chip is active. The
peak-to-peak jitter was measured to be less than 150 ps. This
PLL jitter characteristic is especially important for multiphase

Fig. 18 shows an output data waveform at 960 Mb/s. The
master chip is sending data to the bus according to the
predetermined bus protocol. The jitter at the output data is
larger than the jitter at the charge pump PLL clock due to the
extra modulation effect of supply voltage
uctuation to data

Page 511


Fig. 18. Measured BER at various sampling phase.


mV with an internal eye height of 65 mV. The 24 mV of
amplitude noise is primarily due to ringing from the package
inductance and on-chip output capacitance at the transmitter.


Very high data rates are achievable in CMOS technolo-
gies by making extensive use of parallelism. Using an 8 : 1
demultiplexing at the input and a 8 : 1 multiplexing output
transmitter, we achieved a 4-Gbit/s transceiver while keeping
all internal signals <500 MHz in a 0.5-m process technology.
The fundamental limitations of this approach are the I/O
capacitance (increased due to the parallelism), the sampler
uncertainty, and the phase position accuracy of the multiple
clock phases.

Provisions were made in this design to handle very large
jitter accumulation of 83 ps/3 ns by a fast phase-picking
algorithm. The effectiveness of this architecture critically
depends on the jitter characteristics. Although a CMOS PLL
can potentially exhibit this large jitter due to supply noise,
the measured jitter while operating this transceiver is only 50
ps. This jitter is measured in a realistic noise environment
because of the presence of significant digital switching noise
from the large digital phase picker that can couple onto the
VCO elements. Since the jitter is less than the quantization
error, the advantage of the phase picking is only apparent

when additional noise is induced. This low accumulated jitter
implies that the lower tracking bandwidth of a PLL-based
clock recovery circuit can potentially perform equally. The
design of such a system is nontrivial, and still has challenges
in maintaining small static phase offsets. However, since the
phase picking has significant hardware overhead in the extra
number of input samplers and large digital processing, a PLL
would potentially offer similar performance with lower area
and power.


The authors would like to thank S. Sidiropoulos, B. Am-
rutur, K. Falakshahi, Vitesse Semiconductor, Prof. T. Lee,
Prof. L. Kazovsky, and their research groups for invaluable
discussions and assistance.


[1] C.-K. Yang and M. Horowitz, “A 0.8� m CMOS 2.5 Gbps oversampling
receiver and transmitter for serial links,”IEEE J. Solid-State Circuits,
vol. 31, Dec. 1996.

[2] C. Gray et al., “A sampling technique and its CMOS implementation
with 1-Gb/s bandwidth and 25 ps resolution,”IEEE J. Solid-State
Circuits, vol. 29, Mar. 1994.

[3] J. Maneatis and M. Horowitz, “Precise delay generation using coupled
oscillators,” IEEE J. Solid-State Circuits, vol. 28, pp. 1273–1282, Dec.

[4] K. Lee et al., “A CMOS serial link for fully duplex data commu-
nications,” IEEE J. Solid-State Circuits, vol. 30, pp. 353–364, Apr.

[5] A. Fiedler et al., “A 1.0625Gb/s transceiver with 2�-oversampling and
transmit signal pre-emphasis,” inISSCC’97 Dig. Tech. Papers, Feb.
1997, pp. 238–239.

[6] A. Widmer et al., “Single-chip 4� 500 Mbaud CMOS transceiver,”
IEEE J. Solid-State Circuits, vol. 31, pp. 2004–2014, Dec. 1996.

[7] F. M. Gardner,Phaselock Techniques, 2nd ed. New York: Wiley, 1979.
[8] W. Dally and J. Poulton, “A tracking clock recovery receiver for 4-Gb/s

signaling,” in Hot Interconnect97 Proc., Aug. 1997, p. 157.
[9] S. Sidiropoulos and M. Horowitz, “A semi-digital DLL with unlimited

phase shift capability and 0.08–400MHz operating range,” inISSCC’95
Dig. Tech. Papers, Feb. 1995, pp. 332–333.

[10] J. E. McNamara,Technical Aspects of Data Communication, 2nd ed.
Bedford, MA: Digital, 1982.

[11] S. Kim et al., “An 800Mbps multi-channel CMOS serial link with 3�
oversampling,” inIEEE 1995 CICC Proc., Feb. 1995, p. 451.

[12] M. J. Pelgrom, “Matching properties of MOS transistors,”IEEE J.
Solid-State Circuits, vol. 24, p. 1433, Dec. 1989.

[13] J. A. Crawford, Frequency Synthesizer Design Handbook. Boston,
MA: Artech House, 1994.

[14] J. Proakis,Communication Systems Engineering. Englewood Cliffs,
NJ: Prentice-Hall, 1994.

Chih-Kong Ken Yang (S’93) received the B.S. and
M.S degrees in electrical engineering from Stanford
University, Stanford, CA, in 1992.

He is currently pursuing the Ph.D. degree at
Stanford University in the area of circuit design for
high-speed interfaces.

Mr. Yang is a member of Tau Beta Pi and Phi
Beta Kappa.

Page 512


Ramin Farjad-Rad (S'95) was born in Tehran,
Iran, in 1971. He received the B.Sc. degree in
electrical engineering from Sharif University of
Technology, Tehran, in 1993 and the M.Sc. degree
in electrical engineering from Stanford University,
Stanford, CA, in 1995, where he is currently a Ph.D.
candidate in electrical engineering.

He worked at SUN Microsystems Laboratories,
Mountain View, CA, on a 1.25-Gbit/s serial trans-
ceiver for the �ber channel standard during the
summer of 1995. Over the summer of 1996, he

worked at LSI Logic, Milpitas, CA, where he examined different multi-Gbit/s
serial transceiver architectures.

Mr. Farjad-Rad holds one U.S. patent, and is also the Bronze Medal Winner
of the 20th International Physics Olympiad, Warsaw, Poland.

Mark A. Horowitz (S'77±M'78±SM'95) received
the B.S. and M.S. degrees in electrical engineering
from MIT in 1978, and the Ph.D. degree from
Stanford University, Stanford, CA, in 1984.

He is the Yahoo Founders Professor of Electrical
Engineering and Computer Science at Stanford. His
research area is in digital system design, and he has
led a number of processor designs including MIPS-
X, one of the �rst processors to include an on-chip
instruction cache, TORCH, a statically scheduled,
superscalar processor, and FLASH, a
exible DSM

machine. He has also worked on a number of other chip design areas including
high-speed memory design, high-bandwidth interfaces, and fast
oating point.
In 1990, he took a leave from Stanford to help start Rambus Inc., a company
designing high-bandwidth memory interface technology. His current research
includes multiprocessor design, low-power circuits, memory design, and high-
speed links.

Dr. Horowitz is the recipient of a 1985 Presidential Young Investigator
Award and an IBM Faculty Development Award, as well as the 1993 Best
Paper Award from the International Solid-State Circuits Conference.

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