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TitleFundamentals of Digital Logic and Microcontrollers
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Table of Contents
                            Cover
Title Page
Copyright
Contents
Preface
Chapter 1 Introduction to Digital Systems
	1.1 Explanation of Terms
	1.2 Design Levels
	1.3 Combinational and Sequential Circuits
	1.4 Digital Integrated Circuits
		1.4.1 Diodes
		1.4.2 Transistors
		1.4.3 MOS Transistors
	1.5 Integrated Circuits (ICs)
	1.6 CAD (Computer-Aided Design)
	1.7 Evolution of the Microcontroller
	1.8 Typical Microcontroller Applications
		1.8.1 A Simple Microcontroller Application
		1.8.2 Embedded Controllers
Chapter 2 Number Systems and Codes
	2.1 Number Systems
		2.1.1 General Number Representation
		2.1.2 Converting Numbers from One Base to Another
	2.2 Unsigned and Signed Binary Numbers
	2.3 Codes
		2.3.1 Binary-Coded-Decimal Code (8421 Code)
		2.3.2 Alphanumeric Codes
		2.3.3 Excess-3 Code
		2.3.4 Gray Code
		2.3.5 Unicode
	2.4 Fixed-Point and Floating-Point Representations
	2.5 Arithmetic Operations
		2.5.1 Binary Arithmetic
		2.5.2 BCD Arithmetic
	2.6 Error Correction and Detection
	Questions and Problems
Chapter 3 Boolean Algebra and Digital Logic Gates
	3.1 Basic Logic Operations
		3.1.1 NOT Operation
		3.1.2 OR operation
		3.1.3 AND operation
	3.2 Other Logic Operations
		3.2.1 NOR operation
		3.2.2 NAND operation
		3.2.3 Exclusive-OR operation (XOR)
		3.2.4 Exclusive-NOR Operation (XNOR)
	3.3 IEEE Symbols for Logic Gates
	3.4 Positive and Negative Logic
	3.5 Boolean Algebra
		3.5.1 Boolean Identities
		3.5.2 Simplification Using Boolean Identities
		3.5.3 Consensus Theorem
		3.5.4 Complement of a Boolean Function
	3.6 Standard Representations
	3.7 Karnaugh Maps
		3.7.1 Two-Variable K-map
		3.7.2 Three-Variable K-map
		3.7.3 Four-Variable K-map
		3.7.4 Prime Implicants
		3.7.5 Expressing a Boolean function in Product-of-sums (POS) form using a K-map
		3.7.6 Don't Care Conditions
		3.7.7 Five-Variable K-map
	3.8 Quine-McCluskey Method
	3.9 Implementation of Digital Circuits with NAND, NOR, and Exclusive-OR/Exclusive-NOR Gates
		3.9.1 NAND Gate Implementation
		3.9.2 NOR Gate Implementation
		3.9.3 XOR / XNOR Implementations
	Questions and Problems
Chapter 4 Combinational Logic
	4.1 Basic Concepts
	4.2 Analysis of a Combinational Logic Circuit
	4.3 Design of a Combinational Circuit
	4.4 Multiple-Output Combinational Circuits
	4.5 Typical Combinational Circuits
		4.5.1 Comparators
		4.5.2 Decoders
		4.5.3 Encoders
		4.5.4 Multiplexers
		4.5.5 Demultiplexers
		4.5.6 Binary / BCD Adders and Binary Subtractors
	4.6 IEEE Standard Symbols
	4.7 Read-Only Memories (ROMs)
	4.8 Programmable Logic Devices (PLDs)
	4.9 Commercially Available Field Programmable Devices (FPDs)
	4.10 Hardware Description Language (HDL)
	4.11 Verilog basics
		4.11.1 Verilog keywords
		4.11.2 A typical Verilog Segment
		4.11.3 Verilog operators
		4.11.4 Verilog Constants
		4.11.5 Modeling logical conditions in a circuit
		4.11.6 Verilog if-else and case-endcase structures
		4.11.7 A typical Verilog Simulator
	4.12 Verilog modeling examples for combinational circuits
		4.12.1 Structural modeling
		4.12.2 Dataflow modeling
		4.12.3 Behavioral modeling
	Questions and Problems
Chapter 5 Sequential Logic
	5.1 Basic Concepts
	5.2 Latches and Flip-Flops
		5.2.1 SR Latch
		5.2.2 Gated SR Latch
		5.2.3 Gated D Latch
		5.2.4 Edge-Triggered D Flip-Flop
		5.2.5 JK Flip-Flop
		5.2.6 T Flip-Flop
	5.3 Flip-flop timing parameters for edge-triggered flip-flops
	5.4 Preset and Clear Inputs
	5.5 Summary of the gated SR latch and the Flip-Flops
	5.6 Analysis of Synchronous Sequential Circuits
	5.7 Types of Synchronous Sequential Circuits
	5.8 Minimization of States
	5.9 Design of Synchronous Sequential Circuits
	5.10 Design of Counters
	5.11 Examples of Synchronous Sequential Circuits
		5.11.1 Registers
		5.11.2 Modulo-n Counters
		5.11.3 Random-Access Memory (RAM)
	5.12 Algorithmic State Machines (ASM) Chart
	5.13 Asynchronous Sequential Circuits
	5.14 Verilog description of typical synchronous sequential circuits
	Questions and Problems
Chapter 6 CPU, Memory, and I/O
	6.1 Design of the CPU
		6.1.1 Register Design
		6.1.2 Arithmetic Logic Unit (ALU)
		6.1.3 ALU Design
		6.1.4 Control Unit Design
	6.2 Memory Organization
		6.2.1 Types of Main memory
		6.2.2 READ and WRITE Timing Diagrams
		6.2.3 Main Memory Organization
	6.3 Input/Output (I/O)
		6.3.1 Simple I/O Devices
		6.3.2 Programmed I/O
		6.3.3 Interrupt I/O
	6.4 CPU Design using Verilog
	Questions and Problems
Chapter 7 Microcontroller Basics
	7.1 Basic Blocks of a Microcontroller
		7.1.1 System Bus
		7.1.2 Clock Signals
	7.2 Microcontroller Architectures
	7.3 Basic Concept of Pipelining
	7.4 RISC vs. CISC
	7.5 Functional Representation of a Typical RISC Microcontroller—The PIC18F4321
	7.6 Basics of Programming Languages
		7.6.1 Machine Language
		7.6.2 Assembly Language
		7.6.3 High-Level Language
	7.7 Choosing a Programming Language
	7.8 Introduction to C Language
		7.8.1 Data Types
		7.8.2 Bit Manipulation Operators
		7.8.3 Control Structures
		7.8.4 The switch Construct
		7.8.5 The while Construct
		7.8.6 The for Construct
		7.8.7 The do-while Construct
		7.8.8 Structures and Unions
		7.8.9 Functions in C
		7.8.10 Macros
	Questions and Problems
Chapter 8 PIC18F Hardware and Interfacing Using C: Part 1
	8.1 PIC18F Pins and Signals
		8.1.1 Clock
		8.1.2 PIC18F Reset
		8.1.3 A Simplified Setup for the PIC18F4321
	8.2 PIC18F4321 programmed I/O using C
		8.2.1 PIC 18F4321 I/O ports
		8.2.2 Interfacing LEDs (Light Emitting Diodes) and Seven-segment Displays
		8.2.3 Microchip MPLAB C18 compiler and the PICkit3 interface
		8.2.4 Configuration commands
	8.3 PIC18F Interrupts
		8.3.1 PIC18F Interrupt Types
		8.3.2 PIC18F External Interrupts in Default Mode
		8.3.3 Interrupt Registers and Priorities
		8.3.4 Setting the Triggering Levels of INTn Pin Interrupts
		8.3.5 Programming the PIC18 interrupts using C
	Questions and Problems
Chapter 9 PIC18F Hardware and Interfacing Using C: Part 2
	9.1 PIC18F Timers
		9.1.1 Timer0
		9.1.2 Timer1
		9.1.3 Timer2
		9.1.4 Timer3
	9.2 PIC18F Interface to an LCD (Liquid Crystal Display)
	9.3 Analog Interface
		9.3.1 On-chip A/D Converter
		9.3.2 Interfacing an External D/A (Digital-to-Analog) Converter to the PIC18F4321
	9.4 Serial Interface
		9.4.1 Synchronous Serial Data Transmission
		9.4.2 Asynchronous Serial Data Transmission
		9.4.3 PIC18F Serial I/O
	9.5 PIC18F4321 Capture/Compare/PWM (CCP) Modules
		9.5.1 CCP Registers
		9.5.2 CCP Modules and Associated Timers
		9.5.3 PIC18F4321 Capture Mode
		9.5.4 PIC18F4321 Compare Mode
		9.5.5 PIC18F4321 PWM (Pulse Width Modulation) Mode
	9.6 DC Motor Control
	Questions and Problems
Appendix A: Answers to Selected Problems
Appendix B: Glossary
Appendix C: Tutorial for Compiling and Debugging A C-Program using the MPLAB
Appendix D: Interfacing the PIC18F4321 to a Personal Computer or a Laptop using PICkit™ 3
	D.1 Initial Hardware Setup for the PIC18F4321
	D.2 Connecting the Personal Computer (PC) or the Laptop to the PIC18F4321 Via PICkit3
	D.3 Programming the PIC18F4321 from a Personal Computer or a Laptop using the PICkit3
Bibliography
Credits
Index
End User License Agreement
                        
Document Text Contents
Page 257

Sequential Logic 239

(a) Counting sequence 0, 1, 3, 4, 5, 6, 7, and repeat. Use JK flip-flops.
(b) Counting sequence 0, 2, 3, 4, 6, 7, and repeat. Use D flip-flops.
(c) Counting sequence 0, 1, 2, 4, 5, 6, 7, and repeat. Use T flip-flops.

5.25 Design a 4-bit general-purpose register as follows:

Increment11
Rotate right; (A3 A0 , Ai Ai + 1 for i = 0,1,2)01
Rotate left; (A0 A3 , Ai Ai – 1 for i = 1,2,3)10
Load external data00

FunctionS0S1

Use Figure P5.25 as the building block:

5.26 Design a logic diagram that will generate 19 timing signals. Use a ring counter
with JK flip-flops.

5.27 Consider the 2-bit Johnson counter shown in Figure P5.27. Derive the state
diagram. Assume the D flip-flops are initialized to A = 0 and B = 0.

5.28 Assuming AB = 10, verify that the 2-bit counter shown in Figure P5.28 is a
ring counter. Derive the state diagram.

5.29 What is the basic difference between SRAM and DRAM?

5.30 Given a memory with a 24-bit address and 8-bit word size,
(a) How many bytes can be stored in this memory?
(b) If this memory were constructed from 1K � 1-bit RAM chips, how

many memory chips would be required?

FIGURE P5.25.

0 1 2 3CLK

S

S

CLR

1

0 S

FIGURE P5.27.

Clk

QD

Clk

Q
A B

Clk
Q Q

D

Page 258

240 Fundamentals of Digital Logic and Microcontrollers

FIGURE P5.33.

T
T

T
T

X= X=

y = 0

Z=

0
1

2
3

1 0

1

Z= 0

Y = 1

c = 1

c = 0

5.31 Draw an ASM chart for the following: Assume three states (a, b, c) in the system
with one input x and two registers R1 and R2. The circuit is initially in state a. If
x = 0, the control goes from state a to state b and, clears registers R1 to 0 and sets
R2 to 1, and then moves to state c. On the other hand if x = 1, the control goes
to state c. In state c, R1 is subtracted from R2 and the result is stored in R1. The
control then moves back to state a and the process continues.

5.32 Draw an ASM chart for each of the following sequence of operations:
(a) The ASM chart will define a conditional operation to perform the

operation R2 ← R2 – R1 during State T0 and will transfer control to State
T1 if the control input c is 1; if c=0, the system will stay in T0. Assume
that R1 and R2 are 8-bit registers.

(b) The ASM chart in which the system is initially in State T0 and then
checks a control input c. If c=1, control will move from State T0 to State
T1; if c=0, the system will increment an 8-bit register R by 1 and control
will return to the initial state.

5.33 Draw an ASM chart for the following state diagram of Figure P5.33:
Assume that the system stays in initial state T0 when control input c = 0 and
input X = 1. The sequence of operations is started from T0 when X = 0. When
the system reaches state T3, it stays in T3 indefinitely as long as c = 1; the
system returns to state T0 when c = 0.

FIGURE P5.28.

Clk

Q
A

Clk

J

K Q

Clk

QJ

K Q

B

Page 513

Index 495

V
Verilog, 146–167, 217–234

ALU, 296–298
always, 154, 217–218
assign, 152, 161–163
begin, 151, 163
Behavioral, 155, 163–167, 217–234
Blocking assignment, 219
case, 153
Clock, 218
Combinational circuit design, 155–167
Concatenate operator, 152
Conditional operator, 152
Counter, 225–230
CPU, 299–308
Dataflow, 155, 161–163
$display, 154
$monitor, 154
$time, 153, 154
end, 151
endmodule, 148
Hierarchical, 159–161
if-else, 153, 164
initial, 154, 217
Memory, 296
Miswiring, 152–153
module, 148
Named association, 148–149
Net, 150
Non-blocking assignment, 219
Numbers, 152
Operators, 150, 151–152

parameter, 152, 219
Positional association, 148–149
Procedural statement, 217–218
Reduction operator, 151
reg, 150–151
Register, 230–232
Sequential circuit design, 217–234
Status Register, 232–234
Structural, 155–161
Test bench, 153–154
wire, 150

VHDL, 147
VLSI, 18
Volatile memory, See Memory Types
vonNeumann architecture, 6, 21, 320–321, 449

W
Wired-AND logic, 13
Word, 3, 449
WRITE Timing Diagram, 286–287

X
XNOR. See Exclusive-NOR.
XOR. See Exclusive-OR.
XOR/XNOR Implementation, 102–105

Z
Zero flag, 232, 233

Page 514

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